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|          TECHNICAL REPORT ECE-94-6           |
|                  June 1994                   |
| Dept. of Electrical and Computer Engineering |
|           University of Victoria             |
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TITLE:   A Probabilistic Approach to Timing Analysis for 
	 Synthesis and its Application to Microprocessor 
	 Interface Design

AUTHORS: Marco A. Escalante and Nikitas Dimopoulos

NOTE:    To appear in IEEE Pacific Rim Conference '95

ABSTRACT

Design automation techniques are playing a key role in 
controlling the complexity of system design. Our work is 
inscribed in the design automation of microporcessor-based 
systems which necessitates the design of interfaces for 
system integration. During the interface synthesis it is 
required to validate the timing of a design yet to be 
implemented. In this paper we present an original methodology
of timing analysis that can determine in advance of the 
implementation tight bounds on interface path delays based on 
the given timing information. The so-called timing analysis 
for synthesis provides an attractive alternative to standard 
timing analysis by eliminating the need of iteratively 
producing a circuit and verifying it until the implementation 
satisfies the design constraints. We propose two frameworks 
based on timed Petri nets to tackle the timing analysis 
problem. In the basic framework, interval arithmetic is used 
to pose the timing analysis for synthesis problem as a 
conjunction of linear optimization programs. A generalization 
of the basic framework uses a stochastic model which is 
suitable for reliability analysis.