TITLE: Modeling Timing Correlation and the Accurate Timing
       Verification of Digital Interface Circuits

AUTHORS: Marco A. Escalante and Nikitas J. Dimopoulos

IN:
         Proceedings of the Mid-West Symposium on
         Circuits and Systems,
         Des Moines, Aug. 1996.

ABSTRACT

Recent research on timing verification of digital interface 
circuits has implicitly assumed that the delays of different 
signal transitions in the circuit are independent of one 
another. However timing diagrams in data sheets clearly 
specify correlation information. If timing correlation is 
ignored the results of verification can be overly pessimistic. 
In this paper we propose a probabilistic timed Petri net 
capable of representing timing correlation. For the sub-
class of periodic nets with and and or causality we develop 
a procedure that not only accurately checks if each one of 
the given timing constraints is satisfied but if the check 
fails also determines the probability that a particular
timing constraint would be violated.