TITLE:   A Probabilistic Timing Analysis for Synthesis in
         Microprocessor Interface Design

AUTHORS: Marco A. Escalante and Nikitas J. Dimopoulos

IN:      Proceedings of the IEEE Pacific Rim Conference on
         Communications, Computers and Signal Processing, 
         Victoria, B.C., Canada, May 1995, pp. 277 - 280. 

ABSTRACT

Systems are constructed by connecting simpler modules. 
Interfaces are used to achieve inter-module connectivity. 
This work addresses the problem of verifying the correctness of
the interface timed behavior in advance of its implementation. 
A technique called timing analysis for synthesis (TAFS) models 
the interface path delays as random variables and finds the 
tights bounds on those variables which satisfy the timing 
constraints given in the specifications. Such model allows the 
designer to perform a reliability analysis in addition to 
finding bounds on the timing parameters of the interface design.