TITLE:   Timing Analysis for Synthesis in Microprocessor
         Interface Design

AUTHORS: Marco A. Escalante and Nikitas J. Dimopoulos

IN:      Proc. of the Seventh International Symposium on
         High-Level Synthesis, Niagara-on-the-Lake, Ontario, 
	 Canada, pp. 23 - 28, May 18-20, 1994.

ABSTRACT

Design automation techniques are playing an important role in
controlling the complexity of system design. Our work is 
inscribed in the design automation of microprocessor-based 
systems which necessitates the design of interfaces for system 
integration. During the interface synthesis it is required to 
validate the timing of a design yet to be implemented. In this 
paper we present a novel methodology to timing analysis that 
can determine tight bounds on interface path delays based on 
the given timing information. The timing analysis for synthesis 
problem, a transposition of the constraint satisfaction problem,
is posed as an optimization problem using interval arithmetic 
techniques.