AUTHORS: R. Sivakumar and N. J. Dimopoulos

TITLE:   A 1.2 $\mu m$ CMOS chip for deadlock-free routing in
         Hypercycle Networks

IN:      Proceedings of the IEEE Pacific Rim Conference on 
         Communications, Computers and Signal Processing,
         Victoria, Canada, pp. 505 - 509, May 19-21, 1993

ABSTRACT

In this work, we consider deadlock-free routing in Hypercycles 
which are class of multidimensional graphs used for modeling 
interconnection networks. Hypercycles offer simple routing, 
incremental expansion, variable diameter, enhanced 
fault-tolerance and hence can be tailored specifically to 
the topology of a particular application. This paper deals 
with the hardware implementation of a 1.2mm CMOS chip that 
implements deadlock preventing routing. The chip consists of 
about 20,000 transistors and has an expected throughput of 20 
Million decisions per second.