AUTHORS: B. Huber, K.F. Li, N.J. Dimopoulos, M. Escalante,
         and E. Manning

TITLE:   Modeling Data Transfer Signal Timings in DAME


IN:      Proceedings of the IEEE Pacific Rim Conference on 
         Communications, Computers and Signal Processing,
         Victoria, Canada, pp. 505 - 509, May 19-21, 1993

ABSTRACT

This paper discusses the timing interface design subsystem in
DAME (Design Automation of Microprocessor-based systems using
and Expert system approach). The timing design subsystem ensures
that all the signals produced by the interface between components
meet the required timing specifications. A main goal of the
timing and signal model  is the abstraction of common features
found in the data transfer timings of most components. This
allows relatively few common rules to be used for the interface
design which apply to all components. This paper introduces the
timing and signal model used to specify the data transfer
timing of microprocessor components. Examples of the different
timing protocol templates are given, and the design strategy
used by the timing design subsystem is discussed.