TITLE: VLSI Design of a Modulo-extractor AUTHORS: R. Sivakumar, N. J. Dimopoulos, and K. F. Li IN: Proceedings of the IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Victoria, B.C., Canada, May 1991, vol. 1, pp. 327-330 ABSTRACT In this paper, a VLSI design of a modulo-extractor based on the principles of Residue Arithmetic is discussed. Area-time complexity of the structure is shown to be of $O (N \log N)$. The circuit has been implemented in $3\mu$ CMOS technology and simulation results have yielded a propagation delay of less than 100ns.